Where or when NOT to use FPGAs…

Well, I praised a lot the advantages of FPGAs but for sure there are situations where you would not like to have them, besides there should be some drawbacks in the design methodology and programming approach.

One thing is clear, you have to be prepared for a concept shift when start using them. Human mind is used to think sequentially and CPUs are acting in this way. When programming a CPU in the C language you describe how the program behaves, compile that program and then download it into silicon and let the HW execute it.

When programming FPGAs you directly generate the HW and have no idea about how many resources will be used. Anyhow the existing tools for FPGAs programming, from Xilinx for example, offer some estimations about the number of gates used, but as far as I know there is no statistic info equivalent to memory and clock (let’s say the equivalent of CPU usage) usage estimation. Nevertheless  FPGAs are traditionally known as big resource waster, I will not go here in too many details explaining why … for the moment is not the purpose of this post and so far I do not have enough knowledge to outline this …

Coming back to the idea of concept shift I would like to stress the fact that this brings disadvantages (or advantages, depends on how you would like to see the problem) for both HW and SW engineers. SW should start to have a grasp on HW and should know how programmable logic works, also HW engineers will have to learn HDL languages. But like I previously quoted Michael Barr, this border should be nailed down and both should have at least a general understanding about looks like the other dark half, that’s why I rather consider this more an advantage.

But let’s not move to away from the questions in the title .. I think one good reason where NOT no use them is where there is a big production volume and where the price per unit is essential. I see automotive and mobile communications 2 good candidates for these features. When a company is going to produce several million parts, then sparing even one $ (or 1 euro, as long as we will have euro) can be critical for its budget.

Another place where I would not see them suitable is where power consumption is a critical factor (here also I would like to name again the 2 industry fields). To be honest I am not an expert in this matter but having so much logic circuitry deployed on a single silicon die, it should consume quite a lot. Just taking into account that FPGAs do not have implemented sleep functionality should lead to the same conclusion: take care when you want to use FPGAs where power consumption is a critical factor. There are a couple of useful video tutorials with respect to this on Xilinx web page, maybe it worth having a look out there.

On top of all the things above, I would put also the fact that FPGAs basically need to be re-programmed each time they are powered on. FPGAs are just a matrix of static RAM cells, meaning that their content is gone after supply is removed. In other words, each time they are powered on their configuration is copied from an external memory, non-volatile, into FPGAs. They are practically blind before powering-up, don’t know anything, neither at which frequency they should work, neither which resources will be used, almost nothing …

That’s it for now!


2 Responses to Where or when NOT to use FPGAs…

  1. kellogs says:

    >>On top of all the things above, I would put also the fact that FPGAs basically need to be re-programmed each time they are powered on

    Whoat!? I learn something new everyday 🙂 Never knew that. Btw, what do you make of Mihai Budiu’s work on reconfigurable hardware at M$ ? http://www.cs.cmu.edu/~mihaib/research/research.html#research

    So now I can draw the line: you say that HWists need to learn SW and SWists about HW ? Yipeee I would say, that means i can ask for more cash at job interview. For the employer, however, it means higher costs if i did. So they’ll keep the FPGA team rather short-limbed.

    • Well .. we always learn new things in life … that’s why I stress so much on blurring the line between HW and SW knowledge, not only about making FPGA programmers to ask more $$ 🙂

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