What is statical and dynamical power consumption?

Well, the idea of this post was somehow to introduce a further discussion about intricacies of power management and calculations how to handle all this in FPGAs context.

Basically the difference between the two resides in the state of the transistors that the corresponding IC is made of. Dynamic power consumption refers to power consumed when logic states of transistors are switching, static power refers to power consumed while transistors are in idle state or in other words is the “leakage power”.

So dynamic power dissipation can come from logic activity, whenever the chip is not in standby or in sleep, this is what we also name transient power. I will not go through complicated calculations, since me neither I do not understand them, but I will simply come and saying that this kind of power dissipation strongly depends on supply voltage and clock frequency used

Besides all this there is also what is called short circuit power, which is part of dynamic power dissipation, since is related to the state change of the digital inputs, and is determined by the rise and fall times of digital signals …

Anyhow this topic is too consistent and for sure cannot be outlined in a post, neither in a couple ones…

Nevertheless the most important things to outline are the following:

  1. Total power dissipation = Static power + Dynamic power
  2.  in standby there is only static power dissipation, which depends only on physical characteristics of the silicon die, or on its layout, this is the leakage power … well… obviously due to leakage current
  3. static power depends also on technology used and is strongly related to the level of transistors integration (the more transistors are squeezed in the same die surface, the more power increases … here there should be many more to say … about 90nm technology and many others … blah blah … is a little bit far from the purpose of this blog)
  4. Dynamic power comes from logic states changes, and implies charging and discharging of internal output capacitances of the silicon die.
  5. there is also a component of dynamic power, besides the transient one, due to logic state changes, called short circuit power, which can uselessly also drain some power and mainly is caused by non-zero rise and fall times of digital input signals …
  6. In the end both, static as well as dynamic power, they strongly depend on the frequency and on the supply voltage (power is directly proportional with the voltage squared) … and there will be these two, voltage and frequency, where most of the improvements will have to be done

Given all above … now is time to put them in FPGAs context and to see when can we have lot of power consumption, and what to do to diminish or avoid this ..

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One Response to What is statical and dynamical power consumption?

  1. Pingback: Hands on FPGA power optimization techniques « Bazaar 2.0

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