Hands on FPGA power optimization techniques

Well … enough with introductory talk, let’s have an eye on some power estimation and optimization techniques on FPGAs.

Some important things to have in mind from previous post :

1. Statical power is power consummed when there is no logic activity and is dued to physical nature of silicon devices (90nM, 65nM technology …)

2. Dynamic power consumption comes from logic activity (toggle rate) and may have some components, one of them is short circuit power, another is dued to glitches (unwanted logic states that may appear because of unequal switching times of the inputs)

Obviously the largest between the two is the dynamical one, which depends on capapcitance, supply voltage and frequency of operation as in the relation below:

Is it really difficult to estimate and then to reduce the dynamic power consumption on an FPGA?

Of course that there are different estimation procedures but one of them is based on a default assigned activity rate which consists in the clock percentage the corresponding logic component is toggling. What does this mean? For example for a counter that should count every clock raising (or falling) edge, the LSB (which in fact translates in HW into a flip flop) toggling is 100%, the toggling activity of next LSB will be 50% … and so on …

Reducing it …? I tried to outline below some of the most common techniques:

  1. Use standard components that the FPGA is made of and map the logic design on them. Basic components of FPGAs are block RAM, I/O, DSP slices, LUTs, each of them  having its own power requirements. This is why is better to conceive the design, when writing HDL code, with the idea of power efficency in mind. Depending on how the design is done the synthesizer can infere (generate the corresponding digital block) more power-optimal or not.Ideally the resulted design should be as compact as possible, long and un-necessary tracks should be avoided. As a consequence of this another advice is to use the hard IP blocks that the FPGA suppliers provide on the chip
  2. Do NOT over-constrain your design, do NOT use more time constraints than needed, because the synthesizer will to its best to meet the constraints (described in User Constraints File) and infere the necessary logic creating useless logic structures that will consume un-necessary power.
  3. Active low control signals are NOT desirable because they require an inversion afterwards, in fact is recommandable to restrain as much as possible the number of control signals or to find the means of sharing them accros the overall design. Also is preferable to use rather synchoronous control signals than asynchronous ones.
  4. Use with care modules that  are big consummers, as DCM (digital clock manager) is known to be. This kind of modules should be used at the top level of the hierarchy in order not to be replicated by the synthesis tool … in fact you should NOT trust so much the synthesizer, it is always recommandable to have a look on the generated HW before going to place and route.
  5. Clock gating – with this, power is saved by temporarly disabling the clock signals for registers whose outputs do not affect the global outputs. I recommend you to have this lecture if you want to get more insight about this matter.

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