Hands on FPGA power optimization techniques

Well … enough with introductory talk, let’s have an eye on some power estimation and optimization techniques on FPGAs.

Some important things to have in mind from previous post :

1. Statical power is power consummed when there is no logic activity and is dued to physical nature of silicon devices (90nM, 65nM technology …)

2. Dynamic power consumption comes from logic activity (toggle rate) and may have some components, one of them is short circuit power, another is dued to glitches (unwanted logic states that may appear because of unequal switching times of the inputs)

Obviously the largest between the two is the dynamical one, which depends on capapcitance, supply voltage and frequency of operation as in the relation below:

Is it really difficult to estimate and then to reduce the dynamic power consumption on an FPGA?

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What is statical and dynamical power consumption?

Well, the idea of this post was somehow to introduce a further discussion about intricacies of power management and calculations how to handle all this in FPGAs context.

Basically the difference between the two resides in the state of the transistors that the corresponding IC is made of. Dynamic power consumption refers to power consumed when logic states of transistors are switching, static power refers to power consumed while transistors are in idle state or in other words is the “leakage power”.

So dynamic power dissipation can come from logic activity, whenever the chip is not in standby or in sleep, this is what we also name transient power. I will not go through complicated calculations, since me neither I do not understand them, but I will simply come and saying that this kind of power dissipation strongly depends on supply voltage and clock frequency used

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Where or when NOT to use FPGAs…

Well, I praised a lot the advantages of FPGAs but for sure there are situations where you would not like to have them, besides there should be some drawbacks in the design methodology and programming approach.

One thing is clear, you have to be prepared for a concept shift when start using them. Human mind is used to think sequentially and CPUs are acting in this way. When programming a CPU in the C language you describe how the program behaves, compile that program and then download it into silicon and let the HW execute it.

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Why FPGAs?

Recently I began to ask myself whether FPGAs will start to play a major role in embedded field, in fact in those applications requiring fast processing power, they already have a big word to say.

So, which advantages can they bring into the play? Well I think the answer to this question resides in the short history about foundation of Xilinx company on Wikipedia:

While working for Zilog, Freeman wanted to create chips that acted like a blank tape, allowing users to program the technology themselves. At the time, the concept was paradigm-changing.[5] “The concept required lots of transistors and, at that time, transistors were considered extremely precious – people thought that Ross’s idea was pretty far out”, said Xilinx Fellow Bill Carter, who when hired in 1984 as the first IC designer was the company’s eighth employee

But nowadays silicon became really cheap and that vision practically opened the gates of a new era in which hardware resources could be considered infinite in terms of speed and space … As you may have guessed this implies a significant concept shift, almost completely breaking with the ancient paradigm of microcontroller programming and sequential execution flow of programs, but let’s see what could be the advantages:

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