Hands on FPGA power optimization techniques

Well … enough with introductory talk, let’s have an eye on some power estimation and optimization techniques on FPGAs.

Some important things to have in mind from previous post :

1. Statical power is power consummed when there is no logic activity and is dued to physical nature of silicon devices (90nM, 65nM technology …)

2. Dynamic power consumption comes from logic activity (toggle rate) and may have some components, one of them is short circuit power, another is dued to glitches (unwanted logic states that may appear because of unequal switching times of the inputs)

Obviously the largest between the two is the dynamical one, which depends on capapcitance, supply voltage and frequency of operation as in the relation below:

Is it really difficult to estimate and then to reduce the dynamic power consumption on an FPGA?

Read more of this post


What is statical and dynamical power consumption?

Well, the idea of this post was somehow to introduce a further discussion about intricacies of power management and calculations how to handle all this in FPGAs context.

Basically the difference between the two resides in the state of the transistors that the corresponding IC is made of. Dynamic power consumption refers to power consumed when logic states of transistors are switching, static power refers to power consumed while transistors are in idle state or in other words is the “leakage power”.

So dynamic power dissipation can come from logic activity, whenever the chip is not in standby or in sleep, this is what we also name transient power. I will not go through complicated calculations, since me neither I do not understand them, but I will simply come and saying that this kind of power dissipation strongly depends on supply voltage and clock frequency used

Read more of this post